1. Field of the Invention
The present disclosure relates to comparators, and more particularly, to comparators having reduced size and improved operating speed.
2. Description of the Related Art
A comparator is a circuit device for determining whether two pieces of data, each including a plurality of bits, are identical to each other. The comparator may be used in a circuit for determining whether two pieces of data are identical to each other, a circuit for detecting 0 from digital data, a built-in self test (BIST) circuit, and the like.
FIG. 1 is a circuit diagram of a conventional 8-bit comparator 100. Referring to FIG. 1, the conventional 8-bit comparator 100 compares two pieces of 8-bit data, A [7:0] and B [7:0], and outputs 0 if A [7:0] and B [7:0] are identical to each other and 1 if A [7:0] and B [7:0] are different from each other. The conventional 8-bit comparator 100 includes eight XOR gates, four inversion AND gates, two inversion OR gates, and another inversion AND gate. The eight XOR gates perform an XOR-operation of bits corresponding to the two pieces of 8-bit data A [7:0] and B [7:0]. The four inversion AND gates each perform an inversion AND-operation of outputs of two of the XOR gates of the eight XOR gates. The two inversion OR gates each perform the inversion OR-operation of outputs of two inversion AND gates of the four inversion AND gates. The inversion AND gate performs the inversion AND-operation of outputs of the two inversion OR gates.
The conventional 8-bit comparator 100 outputs 0 if all the bits corresponding to the two pieces of 8-bit data A [7:0] and B [7:0] are identical to one another, and 1 if any one of the bits corresponding to the same bit position in the two pieces of 8-bit data A [7:0] and B [7:0] is different from one another. That is, the conventional 8-bit comparator 100 outputs 0 if the two pieces of 8-bit data A [7:0] and B [7:0] are identical to each other and 1 if the two pieces of 8-bit data A [7:0] and B [7:0] are different from each other.
FIG. 2 is a circuit diagram of a conventional 64-bit comparator 200 using the 8-bit comparator shown in FIG. 1. Several 8-bit comparators are used to compare data having more than 8 bits. For example, 64-bit data can be compared using eight 8-bit comparators. The conventional 64-bit comparator 200 compares two pieces of 64-bit data A [63:0] and B [63:0] and, unlike the 8-bit comparator 100, outputs 1 if A [63:0] and B [63:0] are identical to each other and 0 if A [63:0] and B [63:0] are different from each other. The conventional 64-bit comparator 200 includes eight 8-bit comparators, four inversion OR gates, two inversion AND gates, and an inversion OR gate. The four inversion OR gates perform an inversion OR-operation of outputs of two 8-bit comparators of the eight 8-bit comparators. The two inversion AND gates perform an inversion AND-operation of outputs of two XOR gates of the four inversion OR gates. The inversion OR gate performs the inversion OR-operation of outputs of two exclusive AND gates.
Each conventional 8-bit comparator 100 outputs 0 if the two pieces of 8-bit data A [7:0] and B [7:0] are identical to each other and 1 if the two pieces of 8-bit data A [7:0] and B [7:0] are different from each other. The conventional 64-bit comparator 200 outputs 1 if the conventional 8-bit comparators 100 each output only 0, and 0 if any of the conventional 8-bit comparators 100 outputs a 1. That is, the conventional 64-bit comparator 200 outputs 1 if the two pieces of 64-bit data A [63:0] and B [63:0] are identical to each other, and 0 if the two pieces of 64-bit data A [63:0] and B [63:0] are different from each other.
The conventional 64-bit comparator 200 needs sixty-four XOR gates, forty-two inversion AND gates, and twenty-one inversion OR gates. A lot of logic circuits are required to compare data having more than 64 bits. Thus, a conventional comparator has a large size.
Meanwhile, a time delay required to output results of the conventional 64-bit comparator 200 is Dxor+3Dnand+3Dnor (Dxor is a time delay in an XOR gate, Dnand is a time delay in an inversion AND gate, and Dnor is a time delay in the XOR gate). Thus, the conventional comparator has a relatively slow operating speed.
It is desirable to minimize the size and improve the operating speed of a semiconductor circuit. Therefore, the size of a comparator circuit should be reduced using a smaller number of logic circuits, and the operating speed of the comparator circuit should be improved.